iw4020 b description the IW4020B is ripple - carry binary counter.all counter stages are master - slave flip - flops.the state of a counteradvances one count on the negative transition of each input pulse,a high leve l on the r e s e t line resets the counter to its all zeros state.schmitt trigger action on the input - pulse line permits unlimited rise and fall times features ? operati ng volta g e ra ng e: 3.0 to 18 v ? ? ma x i m u m i n p u t c u rre n t of 1 u a at 18 v o v er fu ll pac k a g e - t e m pera t u re range ; 100 n a a t 18 v a n d 25 c ? ? 16 ? noi s e m ar g i n (o v er fu ll pac k a g e te m perat u re ra ng e): 1.0 v m i n @ 5.0 v s u pp l y 2.0 v m i n @ 10.0 v s u pp l y 2.5 v m i n @ 15.0 v s u pp l y 16 dip - 16 sop - 16 package logic diagra m pin assignment clock 10 9 7 5 4 6 q1 q4 q5 q6 q12 q13 q14 q6 q5 q7 q4 1 2 3 4 5 6 7 16 15 14 13 12 11 10 q11 q10 q8 q9 reset clock 13 q7 q8 gnd 8 9 q1 reset 11 12 14 15 1 2 3 q9 q10 q11 q12 q13 q14 function table i npu ts out pu t clo c k res e t out pu t s tate l n o c ha ng e l a d van c e t o n e xt s t a te pi n 16 = v cc pi n 8 = gnd x h all out p uts a r e l o w x = don ' t care 1 beijing estek electronics co.,ltd
iw4020 b absolute maximum ratings s ymb o l p a r a m e t e r va l u e u n it v c c d c s u p p l y v o lt a g e ( r e f e r e n ce dt o g n d ) - 0 . 5 to + 2 0 v v i n d c i n p u t v o lt a g e ( r e f e r e n ce dt o g n d ) - 0 . 5 t o v c c + 0 . 5 v v o ut dc o u t pu t v ol t a g e (r e f e r e n ce dto gn d ) - 0 . 5 t o v c c + 0 . 5 v i i n d c i n p u t c u rr e n t , p e r p i n + - 1 0 m a p d p o w e r di s s i p a ti o n i n s til l a i r , p l a s ti c d i p + 75 0 50 0 m w p d s o i c p a c k a g e + p o w e r di s s i p a ti o n p e r o u tput tr a n s i s t o r 1 0 0 m w t s tg s t o r a g e t e m p e r a t ure - 6 5 to +1 5 0 ! c t l l ea d t e m pe r a t u r e , 1 m m fr o m c a s e f o r 10 s e c ond s ( p l a s ti c di p o r s o ic p a c k a g e ) 26 0 ! c maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. derating - plastic dip: - 10 mw/ c from 6 5 to 12 5 c soic packag e c from 6 5 to 12 5 c recommended operating conditions s ymbo l p a r a m e te r in m a x u n i t m v c c d c s u p p l y v o l t a g e ( r e f e r e n ce d t o g nd ) 3 . 0 1 8 v v i n , v o ut d c i n p u t v o l t a g e , o u t p u t v o lt a g e ( r e f e r e n ce d t o g nd ) 0 v c c v t o p e r a ti ng t e m p e r a t u r e , a l l p a c k a g e t y p e s - 5 5 + 12 5 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high - impedance circuit. for proper operation, v i n and v ou t should be constrained to the range gnd ( v i n or v ou t ) ? v c c . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc unused outputs must be left open. beijing estek electronics co.,ltd 2
iw4020 b dc ele ctr ic a l c h ara ct e r i st ic s (voltages referenced to gnd) v c c guaranteed limit symbo l parameter test conditions v ? - 5 5 c 2 5 c ? 125 c unit v i h minimum high - level input voltage v i l maximum low - level input voltage v o h minimum high - level v ou t =0.5 v or v c c - 0.5 v v ou t =1.0 v or v c c - 1.0 v v ou t =1.5 v or v c c - 1.5 v v ou t =0.5 v or v c c - 0.5 v v ou t =1.0 v or v c c - 1.0 v v ou t =1.5 v or v c c - 1.5 v 5.0 10 15 5.0 10 15 5.0 3.5 7 11 1.5 3 4 4.95 3.5 7 11 1.5 3 4 4.95 3.5 7 11 1.5 3 4 4.95 v v v output voltag e v i n =gnd or v cc 10 15 9.95 14.95 9.95 14.95 9.95 14.95 v o l maximum low - level output voltag e v i n =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i i n maximum input leakage current i c c maximum quiescent v i n = gnd or v c c 18 v i n = gnd or v c c 5.0 + - 0.1 5 + - 0.1 5 + - 1.0 ? u a 150 supply current (per package) i o l minimum output low (sink) current i o h minimum output high (source) curren t v i n = gnd or v cc v ol =0.4 v v ol =0.5 v v ol =1.5 v v i n = gnd or v cc v o h =4.6 v v o h =2.5 v v o h =9.5 v v o h =13.5 v 10 15 20 5.0 10 15 5.0 5.0 10 15 10 20 100 0.64 1.6 4.2 - 0.64 ? 2.0 ? 1.6 ? 4.2 10 20 100 0.51 1.3 3.4 - 0.51 ? 1.6 ? 1.3 ? 3.4 300 600 3000 0.36 0.9 2.4 - 0.36 ? 1.15 ? 0.9 ? 2.4 u a ma ma 3 beijing estek electronics co.,ltd
iw4020 b ac ele ctr ic a l c h ara ct e r i st ic s s ymbo l p a r a m e t e r (c l =50pf, r l =200 k ? , input t r = t f =20 ns) v c c g u a r a n t e e d l i mit v - 5 5 c 2 5 c 12 5 c u n it f m a x m a xi mu m c l o c k f r e q u e n c y ( f i g u re 1 ) 5 . 0 1 0 1 5 3 . 5 8 1 2 3 . 5 8 1 2 1 . 7 5 4 6 m hz t p l h , t p h l m a x i m um p r o p a g a ti o n d e l a y, c l o c k t o q 1 ( f i gu re 1) t p l h , t p h l m a x i m u m p r o p a g a t i o n d e l a y , q n t o q n + 1 ( f i gu re 3) t p hl m a x i m u m p r o p a g a t i o n d e l a y , r e s e t t o a ny q ( f i gu re 2) t tl h , t t h l m a xi m u m o u tp u t t r a n s i t i o n t i m e , a n y o u t pu t ( f i g u re 1) 5 . 0 1 0 1 5 5 . 0 1 0 1 5 5 . 0 1 0 1 5 5 . 0 1 0 1 5 36 0 16 0 13 0 33 0 8 0 6 0 28 0 12 0 10 0 20 0 10 0 8 0 36 0 16 0 13 0 33 0 8 0 6 0 28 0 12 0 10 0 20 0 10 0 8 0 72 0 32 0 26 0 66 0 16 0 12 0 56 0 24 0 20 0 40 0 20 0 16 0 n s n s n s n s c i n m a xi m u m in p ut c a p a c it a n c e - 7 . 5 p f timing requirements (c l =50pf, r l =200 k ? , input t r = t f =20 ns) v g u a r a nt e e d l i mit s ymbo l p a r a m e t e r v - 5 5 c 2 5 c 12 5 c u n it t w mi n i m u m p u l s e wi d t h , c l o c k ( f i g u re 1 ) 5 . 0 1 0 1 5 t w mi n i m u m p u l s ewi d t h , r e s e t ( f i gu re 2) 5 . 0 1 0 1 5 t r em mi n i m u m r e mov a l ti m e , r e s e t ( f i gu r e 2) 5 . 0 1 0 1 5 14 0 6 0 4 0 20 0 8 0 6 0 35 0 15 0 10 0 14 0 6 0 4 0 20 0 8 0 6 0 35 0 15 0 10 0 28 0 12 0 8 0 40 0 16 0 12 0 70 0 30 0 20 0 n s n s n s t r , t f m a xi m u m i n pu t r i s e a n d f a l l ti m e s , cl o c k ( f i g u re 1) 5 . 0 1 0 1 5 u n li m it e d s 4 beijing estek electronics co.,ltd
iw4020 b clock 90% 50% 10% gnd max tp tp q 90% 50% 10% 90% 50% 10% gnd f igu r e 1 . s wi t c h i n g w a v e for m s clock e 50% gnd reset 50% tp gnd any q 50% gnd f igu r e 2 . s wi t c h i n g w a v e for m s q n 50% tp 50% gnd q n+1 50% gnd f igu r e 3 . s wi t c h i n g w a v e for m s 5 beijing estek electronics co.,ltd
iw4020 b timing diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 clock reset q1 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 expanded logic diagram clock reset q q q q q q 14 q 14 4 14 q 14 r q r r q q 4 q q 14 address : 6a06 -- 6a07 rm 6a07,changyin office building ,no.88,yong ding road,hai dian district ,beijing postalcode:100039 tel: 86 - 010 - 58895780 / 81 / 82 / 83 / 84 fax : 010 - 58895793 http://www.estek.com.cn email:sales@estek.com.cn rev no:01 - 060834 6 beijing estek electronics co.,ltd
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